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1 ? fn8129.0 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-352-6832 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005. all rights reserved all other trademarks mentioned are the property of their respective owners. x51638 cpu supervisor with 16kbit spi eeprom features ? extended power-on reset (800ms nominal) ? selectable watchdog timer ?low v cc detection and reset assertion ?five standard reset threshold voltages ?re-program low v cc reset threshold voltage using special programming sequence ?reset signal valid to v cc = 1v ? determine watchdog or low voltage reset with a volatile flag bit ? long battery life with low power consumption ?<50a max standby current, watchdog on ?<1a max standby current, watchdog off ?<400a max active current during read ? 16kbits of eeprom ? built-in inadvertent write protection ?power-up/power-down protection circuitry ?protect 0, 1/4, 1/2 or all of eeprom array with block lock ? protection ?in circuit programmable rom mode ? 2mhz spi interface modes (0,0 & 1,1) ? minimize eeprom programming time ?32 byte page write mode ?self-timed write cycle ?5ms write cycle time (typical) ? 1.8v to 3.6v, 2.7v to 5.5v and 4.5v to 5.5v power supply operation ? available packages ?14-lead tssop, 8-lead soic description this device combines four popular functions, power- on reset control, watchdog timer, supply voltage supervision, and block lock protect serial eeprom in one package. this combination lowers system cost, reduces board space requirements, and increases reliability. applying power to the device activates a power-on reset circuit which holds reset active for a period of time. this allows the powe r supply and oscillator to stabilize before the processo r can execute code. this device allows 800ms before releasing the controller. the watchdog timer provides an independent protec- tion mechanism for microcontrollers. when the micro- controller fails to restart a timer within a selectable time out interval, the de vice activates the reset sig- nal. the user selects the interval from three preset val- ues. once selected, the interval does not change, even after cycling the power. the x51638 low v cc detection circuitry protects the user?s system from low volt age conditions, resetting the system when v cc falls below the minimum v cc trip point. reset is asserted until v cc returns to proper operating level and stabilizes. five industry standard v trip thresholds are available, however, intersil?s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the thresh- old for applications requiring higher precision. block diagram watchdog timer reset data register command decode & control logic si so sck cs /wdi v cc reset & watchdog timebase power-on and generation v trip + - reset reset low voltage status register protect logic 4kbits 4kbits 8kbits eeprom array watchdog transition detector wp v cc threshold reset logic data sheet march 28, 2005
2 fn8129.0 march 28, 2005 pin configuration pin description pin (soic/pdip) pin tssop name function 11cs /wdi chip select input. cs high, deselects the device and the so output pin is at a high impedance state. unless a nonvolatile write cycle is underway, the device will be in the standby power mode. cs low enables the device, placing it in the active power mode. prior to the start of any operation after power-up, a high to low transition on cs is required watchdog input. a high to low transition on the wdi pin restarts the watchdog timer. the absence of a high to low transition within the watchdog time out pe- riod results in reset going active. 22so serial output. so is a push/pull serial data output pin. a read cycle shifts data out on this pin. the falling edge of the serial clock (sck) clocks the data out. 58si serial input. si is a serial data input pin. input all opcodes, byte addresses, and memory data on this pin. the rising edge of the serial clock (sck) latches the input data. send all opcodes (table 1), addresses and data msb first. 69sck serial clock. the serial clock controls the serial bus timing for data input and output. the rising edge of sck latches in the opcode, address, or data bits present on the si pin. the falling edge of sck changes the data output on the so pin. 36wp write protect. the wp pin works in conjunction with a nonvolatile wpen bit to ?lock? the setting of the watchdog timer control and the memory write protect bits. 47v ss ground 814v cc supply voltage 7 13 reset reset output . reset is an active low open drain output which goes active whenever v cc falls below the minimum v cc sense level. it will remain active until v cc rises above the minimum v cc sense level for 800ms. reset goes active if the watchdog timer is enabled and cs remains either high or low longer than the selectable watchdog time out period. a falling edge of cs will reset the watch- dog timer. reset goes active on power-up at 1v and remains active for 800ms after the power supply stabilizes. 3-5,10-12 nc no internal connections 8-lead soic/pdip cs wp so 1 2 3 4 reset 8 7 6 5 v cc 14-lead tssop so wp v ss 1 2 3 4 5 6 7 reset sck si 14 13 12 11 10 9 8 nc v cc nc x51638 v ss sck si cs nc nc nc nc x51638 x51638
3 fn8129.0 march 28, 2005 principles of operation power-on reset application of power to the x51638 activates a power- on reset circuit. this circuit goes active at v cc sense level (v trip ) and pulls the reset pin low. this signal prevents the system microprocessor from starting to operate with insufficient volt age or prior to stabilization of the oscillator. when v cc exceeds the device v trip value for 800ms (nominal) t he circuit releases reset , allowing the processor to begin executing code. low voltage monitoring during operation, the x51638 monitors the v cc level and asserts reset if supply voltage falls below a pre- set minimum v trip . the reset signal prevents the microprocessor from operating in a power fail or brownout condition. the reset signal remains active until the voltage drops below 1v. it also remains active until v cc returns and exceeds v trip for 800ms. watchdog timer the watchdog timer circuit m onitors the microprocessor activity by monitoring the wdi input. the microproces- sor must toggle the cs /wdi pin periodically to prevent a reset signal. the cs /wdi pin must be toggled from high to low prior to the expiration of the watchdog time out period. the state of two nonvolatile control bits in the status register determine the watchdog timer period. the microprocessor can change these watch- dog bits, or they may be ?locked? by tying the wp pin low and setting the wpen bit high. v cc threshold reset procedure the x51638 is offered with one of several standard v cc threshold (v trip ) voltages. this value will not change over normal operating and storage conditions. however, in applications where the standard v trip is not exactly right, or for higher precision in the v trip value, the x51638 threshold may be adjusted. setting the v trip voltage this procedure sets the v trip to a higher voltage value. for example, if the current v trip is 4.4v and the new v trip is 4.6v, this procedure directly makes the change. if the new settin g is lower than the current setting, then it is necessar y to reset the trip point before setting the new value. to set the new v trip voltage, apply the desired v trip threshold to the v cc pin and tie the cs /wdi pin and the wp pin high. reset and so pins are left uncon- nected. then apply the programming voltage v p to both sck and si and pulse cs /wdi low then high. remove v p and the sequence is complete. figure 1. set v trip voltage resetting the v trip voltage this procedure sets the v trip to a ?native? voltage level. for example, if the current v trip is 4.4v and the v trip is reset, the new v trip is something less than 1.7v. this procedure must be used to set the voltage to a lower value. to reset the v trip voltage, apply a voltage between 2.7 and 5.5v to the v cc pin. tie the cs /wdi pin, the wp pin, and the sck pin high. reset and so pins are left unconnected. then apply the program- ming voltage v p to the si pin only and pulse cs /wdi low then high. remove v p and the sequence is complete. figure 2. reset v trip voltage sck si v p v p cs sck si v cc v p cs x51638
4 fn8129.0 march 28, 2005 figure 3. v trip programming sequence flow chart figure 4. sample v trip reset circuit v trip programming apply 5v to v cc decrement v cc reset pin goes active? measured v trip - desired v trip done execute sequence reset v trip set v cc = v cc applied = desired v trip execute sequence set v trip new v cc applied = old v cc applied + error (v cc = v cc - 50mv) execute sequence reset v trip new v cc applied = old v cc applied - error error < 0 error = 0 yes no error > 0 1 2 3 4 8 7 6 5 x51638 v trip adj. program nc nc v p reset v trip test v trip set v trip nc reset 4.7k 4.7k 10k 10k + x51638
5 fn8129.0 march 28, 2005 spi serial memory the memory portion of the device is a cmos serial eeprom array with intersil?s block lock protection. the array is internally org anized as x 8. the device fea- tures a serial peripheral interface (spi) and software protocol allowing operation on a simple four-wire bus. the device utilizes intersil?s proprietary direct write ? cell, providing a minimu m endurance of 100,000 cycles and a minimum data retention of 100 years. the device is designed to interface directly with the synchronous serial peripheral interface (spi) of many popular microcontroller familie s. it contains an 8-bit instruction register that is accessed via the si input, with data being clocked in on the rising edge of sck. cs must be low during the entire operation. all instructions (table 1), addresses and data are transferred msb first. data input on the si line is latched on the first rising edge of sck after cs goes low. data is outp ut on the so line by the falling edge of sck. sck is static, allowing the user to stop the clock and then start it ag ain to resume operations where left off. write enable latch the device contains a write enable latch. this latch must be set before a write operation is initiated. the wren instruction will set the latch and the wrdi instruction will reset the latc h (figure 3). this latch is automatically reset upon a power-up condition and after the completion of a valid write cycle. status register the rdsr instruction provides access to the status register. the status register may be read at any time, even during a write cycle. t he status register is for- matted as follows: the write-in-progress (wip) bi t is a volatile, read only bit and indicates whether the device is busy with an internal nonvolatile write operation. the wip bit is read using the rdsr instruction. when set to a ?1?, a non- volatile write operation is in progress. when set to a ?0?, no write is in progress. table 1. instruction set note: *instructions are shown msb in leftmost pos ition. instructions are transferred msb first. table 2. block protect matrix 7 65 43210 wpen flb wd1 wd0 bl1 bl0 wel wip instruction name instru ction format* operation wren 0000 0110 set the write enable latch (enable write operations) sflb 0000 0000 set flag bit wrdi/rflb 0000 0100 reset the write enable latch/reset flag bit rsdr 0000 0101 read status register wrsr 0000 0001 write status register (watchdog, block lock, wpen & flag bits) read 0000 0011 read data from memory array beginning at selected address write 0000 0010 write data to memory array beginning at selected address wren cmd status register device pin block block status register wel wpen wp# protected block unprotected block wpen, bl0, bl1 wd0, wd1 0 x x protected protected protected 1 1 0 protected writable protected 1 0 x protected writable writable 1 x 1 protected writable writable x51638
6 fn8129.0 march 28, 2005 the write enable latch (wel ) bit indicates the status of the write enable latch. when wel = 1, the latch is set high and when wel = 0 the latch is reset low. the wel bit is a volatile, read only bit. it can be set by the wren instruction and can be reset by the wrds instruction. the block lock bits, bl0 and bl1, set the level of block lock protection. these nonvolatile bits are pro- grammed using the wrsr instruction and allow the user to protect one quarter, one half, all or none of the eeprom array. any portion of the array that is block lock protected can be read but not written. it will remain protected until the bl bits are altered to disable block lock protection of that portion of memory. the watchdog timer bits, wd0 and wd1, select the watchdog time out period. these nonvolatile bits are programmed with the wrsr instruction. the flag bit shows the status of a volatile latch that can be set and reset by the system using the sflb and rflb instructions. the flag bit is automatically reset upon power-up. this flag can be used by the system to determine whether a reset occurs as a result of a watchdog time out or power failure. the nonvolatile wpen bit is programmed using the wrsr instruction. this bit works in conjunction with the wp pin to provide an in-circuit programmable rom func- tion (table 2). wp is low and wpen bit programmed high disables all status register write operations. in circuit programmable rom mode this mechanism protects the block lock and watchdog bits from inadvertent corruption. in the locked state (programmable rom mode) the wp pin is low and the nonvolatile bit wpen is ?1?. this mode disables nonvolat ile writes to the device?s status register. figure 5. read eepr om array sequence status register bits array addresses protected bl1 bl0 x516x 0 0 none 0 1 $0600?$07ff 1 0 $0400?$07ff 1 1 $0000?$07ff status register bits watchdog time out (typical) wd1 wd0 0 0 1.4 seconds 0 1 600 milliseconds 1 0 400 milliseconds 1 1 disabled 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 7 654321 0 data out cs sck si so msb high impedance instruction 16 bit address 15 14 13 3 2 1 0 x51638
7 fn8129.0 march 28, 2005 setting the wp pin low while wpen is a ?1? while an internal write cycle to the status register is in progress will not stop this write operat ion, but the operation dis- ables subsequent write attempts to the status register. when wp is high, all function s, including nonvolatile writes to the status register operate normally. setting the wpen bit in the status register to ?0? blocks the wp pin function, allowing writes to the status register when wp is high or low. setting the wpen bit to ?1? while the wp pin is low activates the programma- ble rom mode, thus requiring a change in the wp pin prior to subsequent status register changes. this allows manufacturing to in stall the device in a system with wp pin grounded and still be able to program the status register. manufacturing can then load configura- tion data, manufacturing time and other parameters into the eeprom, then set the portion of memory to be protected by setting the block lock bits, and finally set the ?otp mode? by setting the wpen bit. data changes now require a hardware change. read sequence when reading from the eeprom memory array, cs is first pulled low to select the device. the 8-bit read instruction is transmitted to the device, followed by the 16-bit address. after the read opcode and address are sent, the data stored in the memory at the selected address is shifted out on the so line. the data stored in memory at the next address can be read sequen- tially by continuing to provide clock pulses. the address is automatically incremented to the next higher address after each byte of data is shifted out. when the highest address is reached, the address counter rolls over to address $0000 allowing the read cycle to be continued indefinitely. the read operation is terminated by taking cs high. refer to the read eeprom array sequence (figure 1). to read the status register, the cs line is first pulled low to select the device followed by the 8-bit rdsr instruction. after the rdsr opcode is sent, the contents of the status register are shifted out on the so line. refer to the read status r egister sequence (figure 2). write sequence prior to any attempt to write data into the device, the ?write enable? latch (wel) mu st first be set by issuing the wren instruction (figure 3). cs is first taken low, then the wren instruction is clocked into the device. after all eight bits of the in struction are transmitted, cs must then be taken high. if the user continues the write operation without taking cs high after issuing the wren instruction, the wr ite operation will be ignored. to write data to the eeprom memory array, the user then issues the write instru ction followed by the 16 bit address and then the data to be written. any unused address bits are specified to be ?0?s?. the write operation minimally takes 32 clocks. cs must go low and remain low for the duration of the operation. if the address counter reaches the end of a page and the clock continues, the counter will roll back to the first address of the page and overwrite any data that may have been previously written. for the page write operation (byte or page write) to be completed, cs can only be brought high after bit 0 of the last data byte to be written is clocked in. if it is brought high at any other time, the write operation will not be completed (figure 4). to write to the status register, the wrsr instruction is followed by the data to be written (figure 5). data bits 0 and 1 must be ?0?. while the write is in progress following a status regis- ter or eeprom sequence, the status register may be read to check the wip bit. during this time the wip bit will be high. operational notes the device powers-up in the following state: ? the device is in the low power standby state. ? a high to low transition on cs is required to enter an active state and re ceive an instruction. ? so pin is high impedance. ? the write enable latch is reset. ? the flag bit is reset. ? reset signal is active for t purst . data protection the following circuitry has been included to prevent inadverten t writes: ? a wren instruction must be issued to set the write enable latch. ?cs must come high at th e proper clock count in order to start a nonvolatile write cycle. x51638
8 fn8129.0 march 28, 2005 figure 6. read status register sequence figure 7. write enable latch sequence figure 8. write sequence 01234567891011121314 76543210 data out cs sck si so msb high impedance instruction 01234567 cs si sck high impedance so 32 33 34 35 36 37 38 39 sck si cs 012345678910 sck si instruction 16 bit address data byte 1 76543210 cs 40 41 42 43 44 45 46 47 data byte 2 76543210 data byte 3 76543210 data byte n 15 14 13 3 2 1 0 20 21 22 23 24 25 26 27 28 29 30 31 654 321 0 x51638
9 fn8129.0 march 28, 2005 figure 9. status register write sequence symbol table 0123456789 cs sck si so high impedance instruction data byte 765432 10 10 11 12 13 14 15 waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance x51638
10 fn8129.0 march 28, 2005 absolute maximum ratings temperature under bias ................... -65c to +135c storage temperature ............ ............ -65c to +150c voltage on any pin with respect to v ss ...................................... -1.0v to +7v d.c. output current ............................................... 5ma lead temperature (soldering, 10 seconds)........ 300c comment stresses above those liste d under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specifi- cation) is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. d.c. operating characteristics (over the recommended operating condit ions unless otherwise specified.) symbol parameter limits unit test conditions min. typ. max. i cc1 v cc write current (active) 5 ma sck = v cc x 0.1/v cc x 0.9 @ 2mhz, so = open i cc2 v cc read current (active) 0.4 ma sck = v cc x 0.1/v cc x 0.9 @ 2mhz, so = open i sb1 v cc standby current wdt = off 1acs = v cc , v in = v ss or v cc , v cc = 5.5v i sb2 v cc standby current wdt = on 50 a cs = v cc , v in = v ss or v cc , v cc = 5.5v i sb3 v cc standby current wdt = on 20 a cs = v cc , v in = v ss or v cc , v cc = 3.6v i li input leakage current 0.1 10 a v in = v ss to v cc i lo output leakage current 0.1 10 a v out = v ss to v cc v il (1) input low voltage -0.5 v cc x 0.3 v v ih (1) input high voltage v cc x 0.7 v cc + 0.5 v v ol1 output low voltage 0.4 v v cc > 3.3v, i ol = 2.1ma v ol2 output low voltage 0.4 v 2v < v cc 3.3v, i ol = 1ma v ol3 output low voltage 0.4 v v cc 2v, i ol = 0.5ma v oh1 output high voltage v cc - 0.8 v v cc > 3.3v, i oh = -1.0ma v oh2 output high voltage v cc - 0.4 v 2v < v cc 3.3v, i oh = -0.4ma v oh3 output high voltage v cc - 0.2 v v cc 2v, i oh = -0.25ma v ols reset output low voltage 0.4 v i ol = 1ma recommended operating conditions temperature min. max. commercial 0c 70c industrial -40c +85c voltage option supply voltage -1.8 1.8v-3.6v -2.7 or -2.7a 2.7v to 5.5v blank or -4.5a 4.5v-5.5v x51638
11 fn8129.0 march 28, 2005 capacitance t a = +25 c, f = 1mhz, v cc = 5v. notes: (1) v il min. and v ih max. are for reference only and are not tested. (2) this parameter is periodically sampled and not 100% tested. equivalent a.c. load circuit at 5v v cc a.c. test conditions a.c. characteristics (over recommended operating condit ions, unless otherwise specified) serial input timing symbol test max. unit conditions c out (2) output capacitance (so, reset )8pfv out = 0v c in (2) input capacitance (sck, si, cs , wp )6pfv in = 0v 5v output 100pf 5v 3.3k ? reset 30pf 1.64k ? 1.64k ? so input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5 symbol parameter 1.8-3.6v 2.7-5.5v unit min. max. min. max. f sck clock frequency 0 1 0 2 mhz t cyc cycle time 1000 500 ns t lead cs lead time 500 250 ns t lag cs lag time 500 250 ns t wh clock high time 400 200 ns t wl clock low time 400 250 ns t su data setup time 50 50 ns t h data hold time 50 50 ns t ri (3) input rise time 100 100 ns t fi (3) input fall time 100 100 ns t cs cs deselect time 500 500 ns t wc (4) write cycle time 10 10 ms x51638
12 fn8129.0 march 28, 2005 serial input timing serial output timing notes: (3) this parameter is periodically sampled and not 100% tested. (4) t wc is the time from the rising edge of cs after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. sck cs si so msb in t su t ri t lag t lead t h lsb in t cs t fi high impedance symbol parameter 1.8-3.6v 2.7-5.5v unit min. max. min. max. f sck clock frequency 0 1 0 2 mhz t dis output disable time 250 250 ns t v output valid from clock low 400 250 ns t ho output hold time 0 0 ns t ro (3) output rise time 100 100 ns t fo (3) output fall time 100 100 ns x51638
13 fn8129.0 march 28, 2005 serial output timing power-up and po wer-down timing reset output timing note: (5) this parameter is periodically sampled and not 100% tested. symbol parameter min. typ. max. unit v trip reset trip point voltage, x51638-4.5a reset trip point voltage, x51638 reset trip point voltage, x51638-2.7a reset trip point voltage, x51638-2.7 reset trip point voltage, x51638-1.8 4.5 4.25 2.85 2.55 1.7 4.62 4.38 2.92 2.62 1.75 4.75 4.5 3.0 2.7 1.8 v v th (5) v trip hysteresis (high to low vs. low to high v trip voltage) 20 mv t purst power-up reset time out 500 800 1400 ms t rpd (5) v cc detect to reset/output 500 ns t f (5) v cc fall time 100 s t r (5) v cc rise time 100 s v rvalid reset valid v cc 1v sck cs so si msb out msb?1 out lsb out addr lsb in t cyc t v t ho t wl t wh t dis t lag v cc t purst t purst t r t f t rpd reset 0 volts v trip v trip x51638
14 fn8129.0 march 28, 2005 cs /wdi vs. reset timing reset output timing (wd1 = 1, wd0 = 0) reset output timing (wd1 = 0, wd0 = 1) reset output timing (wd1 = 0, wd0 = 0) symbol parameter min. typ. max. unit t wdo watchdog time out period 300 400 550 ms t cst cs pulse width to reset the watchdog 400 ns t rst reset time out 200 400 600 ms symbol parameter min. typ. max. unit t wdo watchdog time out period 450 600 800 ms t cst cs pulse width to reset the watchdog 400 ns t rst reset time out 100 200 300 ms symbol parameter min. typ. max. unit t wdo watchdog time out period 1 1.4 2 sec t cst cs pulse width to reset the watchdog 400 ns t rst reset time out 100 200 300 ms cs /wdi t cst reset t wdo t rst t wdo t rst x51638
15 fn8129.0 march 28, 2005 v trip set conditions v trip reset conditions sck si v p v p cs t vps t vph t p t vps t vph t rp t vpo t vpo t tsu t thd v trip v cc sck si v cc v p cs t vps t vph t p t vps t vp1 t rp t vpo t vpo t tsu t thd v trip v cc x51638
16 fn8129.0 march 28, 2005 table 3. v trip programming specifications v cc = 1.7-5.5v; temperature = 0c to 70c parameter description min. max. unit t vps sck v trip program voltage setup time 1 s t vph sck v trip program voltage hold time 1 s t p v trip program pulse width 1 s t tsu v trip level setup time 10 s t thd v trip level hold (stable) time 10 ms t wc v trip write cycle time 10 ms t rp v trip program cycle recovery period (between successive programming cycles) 10 ms t vpo sck v trip program voltage off time before next cycle 0 ms vp programming voltage 15 18 v v trip v trip programed voltage 1.7 5.0 v vta v trip programed voltage accuracy (v cc applied?v trip ) -0.3 +0.3 v vtr v trip programed voltage repeatability (su ccessive program operations) -5 +5 mv v trip programming parameters are periodically sampled and are not 100% tested. x51638
17 fn8129.0 march 28, 2005 packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 - 8 x 45 8-lead plastic small outline gull wing package type s note: all dimensions in inches (in parentheses in millimeters) 0.250" 0.050"typical 0.050" typical 0.030" typical 8 places footprint x51638
18 fn8129.0 march 28, 2005 packaging information note: all dimensions in inches (in parentheses in millimeters) 14-lead plastic, tsso p, package type v see detail ?a? .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0 - 8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x) x51638
19 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8129.0 march 28, 2005 ordering information part mark information v cc range v trip range package operating temperature range part number reset (active low) 4.5-5.5v 4.5-4.75 8-pi n pdip 0-70c x51638p-4.5a 8l soic 0-70c x51638s8-4.5a -40-85c x51638s8i-4.5a 4.5-5.5v 4.25-4.5 8-pin pdip 0-70c x51638p 8l soic 0-70c x51638s8 -40-85c x51638s8i 14l tssop 0-70c x51638v14 2.7-5.5v 2.85-3.0 8l soic 0-70c x51638s8-2.7a -40-85 o c x51638s8i-2.7a 14l tssop 0-70c x51638v14-2.7a 2.7-5.5v 2.55-2.7 8l soic 0-70c x51638s8-2.7 14l tssop 0-70c x51638v14-2.7 1.8-3.6v 1.7-1.8v 8l soic 0-70c x51638s8-1.8 14l tssop 0?70c x51638v14-1.8 p = 8-pin dip blank = 8-lead soic v = 14 lead tssop blank = 5v 10%, 0c to +70c, v trip = 4.25-4.5 al = 5v10%, 0c to +70c, v trip = 4.5-4.75 i = 5v 10%, -40c to +85c, v trip = 4.25-4.5 am = 5v 10%, -40c to +85c, v trip = 4.5-4.75 f = 2.7v to 5.5v, 0c to +70c, v trip = 2.55-2.7 an = 2.7v to 5.5v, 0c to +70c, v trip = 2.85-3.0 g = 2.7v to 5.5v, -40c to +85c, v trip = 2.55-2.7 ap = 2.7v to 5.5v, -40c to +85c, v trip = 2.85-3.0 ag = 1.8v to 3.6v, 0c to +70c, v trip = 1.7-1.8 ah = 1.8v to 3.6v, -40c to +85c, v trip = 1.7-1.8 w x51638 x x51638

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